library ieee;
library altera;
use altera.altera_primitives_components.all;
use ieee.std_logic_1164.all;
entity qaz is
port( x,b,y,c,clk,clrn,prn:in std_logic;
a:out std_logic);
end qaz;
architecture a of qaz is
component jkff
port(
j,k,clk,clrn,prn:in std_logic;
q:out std_logic);
end component;
component CLOCK123
port( CLK:in std_logic;
CLKOUT:out std_logic);
end component;
signal S1:std_logic;
signal S2:std_logic;
signal clk123:std_logic;
begin
S1<=(x and b)or(not y and c);
S2<=(not b and y)or c;
w1:CLOCK123 port map(clk,clk123);
w2:jkff port map(S1,S2,clk123,clrn,prn,a);

end a;

-------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity CLOCK123 is
port( CLK:in std_logic;
CLKOUT:out std_logic);
end CLOCK123;
architecture a of CLOCK123 is
signal CNT:std_logic_vector(23 downto 0);
begin
process(CLK)
begin
if(CLK'EVENT AND CLK='1')then
if CNT=15999999 then CNT<=(others=>'0');
else CNT<=CNT+1;
end if;
end if;
CLKOUT<=CNT(23);
end process;
end a;