library ieee;
use ieee.std_logic_1164.all;
entity JKFF123 is
port(
S,R,clk:in std_logic;
Q,Qbar:out std_logic);
end JKFF123;
architecture a of JKFF123 is
signal Qt:std_logic;
signal X:std_logic_vector(1 downto 0);
begin
X<=S&R;
process(X)
begin
if(clk'event and clk='1')then
case X is
when "00"=>Qt<=Qt;
when "01"=>Qt<='0';
when "10"=>Qt<='1';
when "11"=>Qt<=not Qt;
end case;
end if;
end process;
Q<=Qt;
Qbar<=not Qt;
end a;