library ieee;
use ieee.std_logic_1164.all;
entity DLatch is
port(
D:in std_logic;
Q,Qbar:out std_logic);
end DLatch;
architecture a of DLatch is
component SRLatch
port(
S,R:in std_logic;
Q,Qbar:out std_logic);
end component;
signal S1:std_logic;
begin
S1<=not D;
w1:SRLatch port map(S=>D,R=>S1,Q=>Q,Qbar=>Qbar);
end a;

-----------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
entity SRLatch is
port(
S,R:in std_logic;
Q,Qbar:out std_logic);
end SRLatch;
architecture a of SRLatch is
signal Qt:std_logic;
signal X:std_logic_vector(1 downto 0);
begin
X<=S&R;
process(X)
begin
case X is
when "00"=>Qt<=Qt;
when "01"=>Qt<='0';
when "10"=>Qt<='1';
when "11"=>Qt<=Qt;
end case;
end process;
Q<=Qt;
Qbar<=not Qt;

end a;