library ieee;
use ieee.std_logic_1164.all;
entity JKLatch is
port(
J,K:in std_logic;
Q,Qbar:out std_logic);
end JKLatch;
architecture a of JKLatch is
component SRLatch
port(
S,R:in std_logic;
Q,Qbar:out std_logic);
end component;
signal S1,S2,S3,S4:std_logic;
begin
S3<=J and S2;
S4<=K and S1;
w1:SRLatch port map(S=>S3,R=>S4,Q=>S1,Qbar=>S2);
Q<=S1;
Qbar<=S2;
end a;

library ieee;
use ieee.std_logic_1164.all;
entity SRLatch is
port(
S,R:in std_logic;
Q,Qbar:out std_logic);
end SRLatch;
architecture a of SRLatch is
signal Qt:std_logic;
signal X:std_logic_vector(1 downto 0);
begin
X<=S&R;
process(X)
begin
case X is
when "00"=>Qt<=Qt;
when "01"=>Qt<='0';
when "10"=>Qt<='1';
when "11"=>Qt<=Qt;
end case;
end process;
Q<=Qt;
Qbar<=not Qt;

end a;