library ieee;
use ieee.std_logic_1164.all;
entity MSFF is
port(
S,R,C:in std_logic;
Q,Qbar,Y:out std_logic);
end MSFF;
architecture a of MSFF is
component SREN
port(
S,R,EN:in std_logic;
Q,Qbar:out std_logic);
end component;
signal S2,S3:std_logic;
begin
w1:SREN port map(S=>S,R=>R,EN=>C,Q=>S2,Qbar=>S3);
w2:SREN port map(S=>S2,R=>S3,EN=>not C,Q=>Q,Qbar=>Qbar);
Y<=S2;
end a;

-------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
entity SREN is
port(
S,R,EN:in std_logic;
Q,Qbar:out std_logic);
end SREN;
architecture a of SREN is
component SRLatch
port(
S,R:in std_logic;
Q,Qbar:out std_logic);
end component;
signal S1,S2:std_logic;
begin
S1<=S and EN;
S2<=R and EN;
w1:SRLatch port map(S=>S1,R=>S2,Q=>Q,Qbar=>Qbar);
end a;

------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
entity SRLatch is
port(
S,R:in std_logic;
Q,Qbar:out std_logic);
end SRLatch;
architecture a of SRLatch is
signal Qt:std_logic;
signal X:std_logic_vector(1 downto 0);
begin
X<=S&R;
process(X)
begin
case X is
when "00"=>Qt<=Qt;
when "01"=>Qt<='0';
when "10"=>Qt<='1';
when "11"=>Qt<=Qt;
end case;
end process;
Q<=Qt;
Qbar<=not Qt;

end a;