/*-----主程式------test.vhd*/
library ieee;
library altera;
use ieee.std_logic_1164.all;
entity test is
port(
clk:in std_logic;
a,b,c,d,e,f,g,s7:out std_logic);
end test;
architecture a of test is
COMPONENT BCD
port(
clk:in std_logic;
Y:out std_logic_vector(3 downto 0));
END COMPONENT;
COMPONENT M1
port( CLK:in std_logic;
CLKOUT:out std_logic); 
END COMPONENT;
COMPONENT seg7
port(Din :in std_logic_vector(3 downto 0);
a,b,c,d,e,f,g,s7:out std_logic);
END COMPONENT;
signal clock:std_logic;
signal temp:std_logic_vector(3 downto 0);
begin
w1:M1 port map(clk,clock);
w2:BCD port map(clock,temp);
w3:seg7 port map(temp,a,b,c,d,e,f,g,s7);
end a;

/*-----除頻器------M1.vhd*/

/*-----BCD------BCD.vhd*/
library ieee;
library altera;
use altera.altera_primitives_components.all;
use ieee.std_logic_1164.all;
entity BCD is
port(
clk:in std_logic;
Y:out std_logic_vector(3 downto 0));
end BCD;
architecture a of BCD is
COMPONENT TFF
   PORT (t   : IN STD_LOGIC;
        clk  : IN STD_LOGIC;
        q    : OUT STD_LOGIC);
END COMPONENT;
signal a,b,c,d,e,f,g,h,i,j:std_logic;
begin

b<=(not j)and a;
e<=a and d;
g<=(a and d) and f;
h<=a and j;
i<=g or h;
w0:TFF port map('1',clk,a);
w1:TFF port map( b ,clk,d);
w2:TFF port map( e ,clk,f);
w3:TFF port map( i ,clk,j);

Y(0)<=a;
Y(1)<=d;
Y(2)<=f;
Y(3)<=j;

end a;

/*-----------seg7.vhd*/

library ieee;
use ieee.std_logic_1164.all;
entity seg7 is
port(Din :in std_logic_vector(3 downto 0);
a,b,c,d,e,f,g,s7:out std_logic);
end seg7;
architecture a of seg7 is
begin
process(Din)
begin
s7<='1';
case Din is
when "0000" =>a<='0';b<='0';c<='0';d<='0';e<='0';f<='0';g<='1';
when "0001" =>a<='1';b<='0';c<='0';d<='1';e<='1';f<='1';g<='1';
when "0010" =>a<='0';b<='0';c<='1';d<='0';e<='0';f<='1';g<='0';
when "0011" =>a<='0';b<='0';c<='0';d<='0';e<='1';f<='1';g<='0';
when "0100" =>a<='1';b<='0';c<='0';d<='1';e<='1';f<='0';g<='0';
when "0101" =>a<='0';b<='1';c<='0';d<='0';e<='1';f<='0';g<='0';
when "0110" =>a<='0';b<='1';c<='0';d<='0';e<='0';f<='0';g<='0';
when "0111" =>a<='0';b<='0';c<='0';d<='1';e<='1';f<='1';g<='1';
when "1000" =>a<='0';b<='0';c<='0';d<='0';e<='0';f<='0';g<='0';
when "1001" =>a<='0';b<='0';c<='0';d<='0';e<='1';f<='0';g<='0';
when others =>a<='1';b<='1';c<='1';d<='1';e<='1';f<='1';g<='1';
end case;
end process;
end a;