有一控制線 S=0計數器做上數 S=1做下數

library ieee;
library altera;
use altera.altera_primitives_components.all;
use ieee.std_logic_1164.all;
entity bit3TFFSynCounter is
port(
s,clrn,prn,clk : in std_logic;
Q : out std_logic_vector(2 downto 0));
end bit3TFFSynCounter;
architecture a of bit3TFFSynCounter is
signal a,b,c,Tb,Ta:std_logic;
component tff
port(
t,clk,clrn,prn : in std_logic;
q : out std_logic);
end component;
begin
w1:tff port map('1',clk,clrn,prn,c);
Tb<=((not s)and(not c))or(s and c);
w2:tff port map(Tb,clk,clrn,prn,b);
Ta<=((not s)and (not b)and(not c))or(s and c and b);
w3:tff port map(Ta,clk,clrn,prn,a);
Q<=a&b&c;
end a;