library ieee;
library altera;
use altera.altera_primitives_components.all;
use ieee.std_logic_1164.all;

entity bit3_ripple is
port( clock,clrn,prn : in std_logic;
Q : out std_logic_vector(2 downto 0) );
end bit3_ripple;

architecture a of bit3_ripple is
signal clk,Ta,Tb:std_logic;

COMPONENT JKFF
PORT( j : IN STD_LOGIC;
k : IN STD_LOGIC;
clk : IN STD_LOGIC;
clrn : IN STD_LOGIC;
prn : IN STD_LOGIC;
q : OUT STD_LOGIC);
END COMPONENT;

COMPONENT M1
port( CLK:in std_logic;
CLKOUT:out std_logic);
END COMPONENT;

begin
w0:JKFF port map( '1', '1' , clk , clrn , prn , Ta );
w1:JKFF port map( '1', '1' , Ta , clrn , prn , Tb );
w2:JKFF port map( '1', '1' , Tb , clrn , prn , Q(2) );

w4:M1 port map(clock,clk);
Q(0)<=Ta;
Q(1)<=Tb;
end a;

---------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity M1 is
port( CLK:in std_logic;
CLKOUT:out std_logic);
end M1;
architecture a of M1 is
signal CNT:std_logic_vector(26 downto 0);
begin
process(CLK)
begin
if(CLK'EVENT AND CLK='1')then
if CNT=79999999 then CNT<=(others=>'0');
else CNT<=CNT+1;
end if;
end if;
CLKOUT<=CNT(26);
end process;
end a;