library ieee;
library altera;
use altera.altera_primitives_components.all;
use ieee.std_logic_1164.all;

entity RSR is
port(
Di:in std_logic;
clock:in std_logic;
clrn : IN STD_LOGIC;
prn : IN STD_LOGIC;
out0,out1,out2,out3:out std_logic);
end RSR;

architecture a of RSR is
signal Sa,Sb,Sc,clk:std_logic;

COMPONENT DFF
PORT (d : IN STD_LOGIC;
clk : IN STD_LOGIC;
clrn : IN STD_LOGIC;
prn : IN STD_LOGIC;
q : OUT STD_LOGIC );
END COMPONENT;

COMPONENT M1
port( CLK:in std_logic;
CLKOUT:out std_logic);
END COMPONENT;

begin
w3:M1 port map(clock,clk);
w4:dff port map(Di,clk,clrn,prn,Sa);
w5:dff port map(Sa,clk,clrn,prn,Sb);
w6:dff port map(Sb,clk,clrn,prn,Sc);
w7:dff port map(Sc,clk,clrn,prn,out0);
out3<=Sa;
out2<=Sb;
out1<=Sc;
end a;