<![CDATA[<a href="http://xn--riqt04ainam61a0lu.xn--0xvu13aevkvkm.tw"><img src="http://www.taigadit.com/usr/logo/logo-00016830-20090306100758.gif" alt="http://痞客丹尼斯.的部落格.tw"></a><br><br>:: 痞客邦 PIXNET ::]]> http://denisueng.pixnet.net/blog http://痞客丹尼斯.的部落格.tw ]]> Fri, 10 Apr 2009 01:47:16 +0000 denisueng@not-valid.com (denisueng) Copyright 2003-2009 denisueng,Pixnet Digital Media Coporation. All rights reserved. PIXNET Media Digital Coporation zh http://blogs.law.harvard.edu/tech/rss <![CDATA[2008-04-11--moore model]]> http://denisueng.pixnet.net/blog/post/23200759 http://denisueng.pixnet.net/blog/post/23200759 library ieee;
library altera;
use altera.altera_primitives_components.all;
use ieee.std_logic_1164.all;
entity qaz is
(Read More...)
]]> Fri, 10 Apr 2009 01:47:16 +0000 VHDL http://denisueng.pixnet.net/blog/post/23200759#comments <![CDATA[2008-03-21--正緣觸發JK正反器]]> http://denisueng.pixnet.net/blog/post/22897129 http://denisueng.pixnet.net/blog/post/22897129 library ieee;
use ieee.std_logic_1164.all;
entity JKFF123 is
port(
S,R,clk:in std_logic;
(Read More...)
]]> Fri, 20 Mar 2009 02:54:51 +0000 VHDL http://denisueng.pixnet.net/blog/post/22897129#comments <![CDATA[2008-03-14--DLatch]]> http://denisueng.pixnet.net/blog/post/22773547 http://denisueng.pixnet.net/blog/post/22773547 library ieee;
use ieee.std_logic_1164.all;
entity DLatch is
port(
D:in std_logic;
(Read More...)
]]> Fri, 13 Mar 2009 01:49:20 +0000 VHDL http://denisueng.pixnet.net/blog/post/22773547#comments <![CDATA[2008-03-14--JKLatch]]> http://denisueng.pixnet.net/blog/post/22773387 http://denisueng.pixnet.net/blog/post/22773387 library ieee;
use ieee.std_logic_1164.all;
entity JKLatch is
port(
J,K:in std_logic;
(Read More...)
]]> Fri, 13 Mar 2009 01:23:37 +0000 VHDL http://denisueng.pixnet.net/blog/post/22773387#comments <![CDATA[2008-03-21--Master-Slave Flip-Flop]]> http://denisueng.pixnet.net/blog/post/22773373 http://denisueng.pixnet.net/blog/post/22773373 library ieee;
use ieee.std_logic_1164.all;
entity MSFF is
port(
S,R,C:in std_logic;
(Read More...)
]]> Fri, 13 Mar 2009 01:20:18 +0000 VHDL http://denisueng.pixnet.net/blog/post/22773373#comments <![CDATA[[報告]數位系統實驗-計數器]]> http://denisueng.pixnet.net/blog/post/22719497 http://denisueng.pixnet.net/blog/post/22719497  數位系統實驗.rar (55.55 KB)


(Read More...)
]]> Tue, 10 Mar 2009 06:56:32 +0000 VHDL http://denisueng.pixnet.net/blog/post/22719497#comments <![CDATA[2008-06-06--利用七段顯示器製作BCD計數器]]> http://denisueng.pixnet.net/blog/post/22719194 http://denisueng.pixnet.net/blog/post/22719194 /*-----主程式------test.vhd*/
library ieee;
library altera;
use ieee.std_logic_1164.all;
entity test is
(Read More...)
]]> Tue, 10 Mar 2009 06:41:37 +0000 VHDL http://denisueng.pixnet.net/blog/post/22719194#comments <![CDATA[2008-06-06--七段顯示器]]> http://denisueng.pixnet.net/blog/post/22719190 http://denisueng.pixnet.net/blog/post/22719190 library ieee;
use ieee.std_logic_1164.all;
entity seg7 is
port(Din :in std_logic_vector(3 downto 0);
a,b,c,d,e,f,g,s7:out std_logic);
(Read More...)
]]> Tue, 10 Mar 2009 06:41:25 +0000 VHDL http://denisueng.pixnet.net/blog/post/22719190#comments <![CDATA[2008-05-29--使用內建TFF實作3-bit Synchronous Counter]]> http://denisueng.pixnet.net/blog/post/22719187 http://denisueng.pixnet.net/blog/post/22719187 有一控制線 S=0計數器做上數 S=1做下數


library ieee;
library altera;
use altera.altera_primitives_components.all;

(Read More...)
]]> Tue, 10 Mar 2009 06:41:09 +0000 VHDL http://denisueng.pixnet.net/blog/post/22719187#comments <![CDATA[2008-05-23--使用內建JKFF實做 3-bit 下數 ripple counter(5second 1次)]]> http://denisueng.pixnet.net/blog/post/22719183 http://denisueng.pixnet.net/blog/post/22719183 library ieee;
library altera;
use altera.altera_primitives_components.all;
use ieee.std_logic_1164.all;

entity bit3_ripple is

(Read More...)
]]> Tue, 10 Mar 2009 06:40:57 +0000 VHDL http://denisueng.pixnet.net/blog/post/22719183#comments <![CDATA[2008-05-16--串聯輸入-並聯輸出(串聯輸出) 右移暫存器]]> http://denisueng.pixnet.net/blog/post/22719180 http://denisueng.pixnet.net/blog/post/22719180 library ieee;
library altera;
use altera.altera_primitives_components.all;
use ieee.std_logic_1164.all;

entity RSR is

(Read More...)
]]> Tue, 10 Mar 2009 06:40:39 +0000 VHDL http://denisueng.pixnet.net/blog/post/22719180#comments <![CDATA[2008-05-16--D型正反器配合多工器構成的並聯-串聯輸出右移暫存器]]> http://denisueng.pixnet.net/blog/post/22719177 http://denisueng.pixnet.net/blog/post/22719177 library ieee;
library altera;
use altera.altera_primitives_components.all;
use ieee.std_logic_1164.all;
entity RSR2 is
(Read More...)
]]> Tue, 10 Mar 2009 06:40:25 +0000 VHDL http://denisueng.pixnet.net/blog/post/22719177#comments <![CDATA[2008-05-09--reg_4bit]]> http://denisueng.pixnet.net/blog/post/22719174 http://denisueng.pixnet.net/blog/post/22719174 library ieee;
library altera;
use altera.altera_primitives_components.all;
use ieee.std_logic_1164.all;
entity reg_4bit is
(Read More...)
]]> Tue, 10 Mar 2009 06:40:07 +0000 VHDL http://denisueng.pixnet.net/blog/post/22719174#comments <![CDATA[2008-05-09--3-bit 並聯載入暫存器(5秒閃一次)]]> http://denisueng.pixnet.net/blog/post/22719171 http://denisueng.pixnet.net/blog/post/22719171 library ieee;
library altera;
use altera.altera_primitives_components.all;
use ieee.std_logic_1164.all;

entity reg_3bit is

(Read More...)
]]> Tue, 10 Mar 2009 06:39:48 +0000 VHDL http://denisueng.pixnet.net/blog/post/22719171#comments <![CDATA[2008-04-16--Mealy Model]]> http://denisueng.pixnet.net/blog/post/22719169 http://denisueng.pixnet.net/blog/post/22719169 library ieee;
library altera;
use altera.altera_primitives_components.all;
use ieee.std_logic_1164.all;
entity Mealy1 is
(Read More...)
]]> Tue, 10 Mar 2009 06:39:36 +0000 VHDL http://denisueng.pixnet.net/blog/post/22719169#comments <![CDATA[2008-04-11--moore model]]> http://denisueng.pixnet.net/blog/post/22719164 http://denisueng.pixnet.net/blog/post/22719164 library ieee;
library altera;
use altera.altera_primitives_components.all;
use ieee.std_logic_1164.all;
entity qaz is
(Read More...)
]]> Tue, 10 Mar 2009 06:39:24 +0000 VHDL http://denisueng.pixnet.net/blog/post/22719164#comments <![CDATA[2008-03-28--除以2的24次方的除頻電路(一秒閃一次)]]> http://denisueng.pixnet.net/blog/post/22719150 http://denisueng.pixnet.net/blog/post/22719150 library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity M1 is
port( CLK:in std_logic;
(Read More...)
]]> Tue, 10 Mar 2009 06:37:51 +0000 VHDL http://denisueng.pixnet.net/blog/post/22719150#comments <![CDATA[2008-03-21--正緣觸發JK正反器]]> http://denisueng.pixnet.net/blog/post/22719146 http://denisueng.pixnet.net/blog/post/22719146 library ieee;
use ieee.std_logic_1164.all;
entity JKFF123 is
port(
S,R,clk:in std_logic;
(Read More...)
]]> Tue, 10 Mar 2009 06:37:35 +0000 VHDL http://denisueng.pixnet.net/blog/post/22719146#comments <![CDATA[2008-03-21--WEEK125]]> http://denisueng.pixnet.net/blog/post/22719124 http://denisueng.pixnet.net/blog/post/22719124 library ieee;
use ieee.std_logic_1164.all;
entity week125 is
port(
clk,j,k:in std_logic;
(Read More...)
]]> Tue, 10 Mar 2009 06:35:11 +0000 VHDL http://denisueng.pixnet.net/blog/post/22719124#comments <![CDATA[2008-03-21--Master-Slave Flip-Flop]]> http://denisueng.pixnet.net/blog/post/22719119 http://denisueng.pixnet.net/blog/post/22719119 library ieee;
use ieee.std_logic_1164.all;
entity MSFF is
port(
S,R,C:in std_logic;
(Read More...)
]]> Tue, 10 Mar 2009 06:34:52 +0000 VHDL http://denisueng.pixnet.net/blog/post/22719119#comments