:: 痞客邦 PIXNET ::

2008-04-11--moore model

2009-04-10T09:47:16+08:00

library ieee;
library altera;
use altera.altera_primitives_components.all;
use ieee.std_logic_1164.all;
entity qaz is

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2008-03-21--正緣觸發JK正反器

2009-03-20T10:54:51+08:00

library ieee;
use ieee.std_logic_1164.all;
entity JKFF123 is
port(
S,R,clk:in std_logic;

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2008-03-14--DLatch

2009-03-13T09:49:20+08:00

library ieee;
use ieee.std_logic_1164.all;
entity DLatch is
port(
D:in std_logic;

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2008-03-14--JKLatch

2009-03-13T09:23:37+08:00

library ieee;
use ieee.std_logic_1164.all;
entity JKLatch is
port(
J,K:in std_logic;

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2008-03-21--Master-Slave Flip-Flop

2009-03-13T09:20:18+08:00

library ieee;
use ieee.std_logic_1164.all;
entity MSFF is
port(
S,R,C:in std_logic;

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[報告]數位系統實驗-計數器

2009-03-10T14:56:32+08:00

數位系統實驗.rar (55.55 KB)

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2008-06-06--利用七段顯示器製作BCD計數器

2009-03-10T14:41:37+08:00

/*-----主程式------test.vhd*/
library ieee;
library altera;
use ieee.std_logic_1164.all;
entity test is

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2008-06-06--七段顯示器

2009-03-10T14:41:25+08:00

library ieee;
use ieee.std_logic_1164.all;
entity seg7 is
port(Din :in std_logic_vector(3 downto 0);
a,b,c,d,e,f,g,s7:out std_logic);

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2008-05-29--使用內建TFF實作3-bit Synchronous Counter

2009-03-10T14:41:09+08:00

有一控制線 S=0計數器做上數 S=1做下數

library ieee;
library altera;
use altera.altera_primitives_components.all;

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2008-05-23--使用內建JKFF實做 3-bit 下數 ripple counter(5second 1次)

2009-03-10T14:40:57+08:00

library ieee;
library altera;
use altera.altera_primitives_components.all;
use ieee.std_logic_1164.all;

entity bit3_ripple is

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2008-05-16--串聯輸入-並聯輸出(串聯輸出) 右移暫存器

2009-03-10T14:40:39+08:00

library ieee;
library altera;
use altera.altera_primitives_components.all;
use ieee.std_logic_1164.all;

entity RSR is

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2008-05-16--D型正反器配合多工器構成的並聯-串聯輸出右移暫存器

2009-03-10T14:40:25+08:00

library ieee;
library altera;
use altera.altera_primitives_components.all;
use ieee.std_logic_1164.all;
entity RSR2 is

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2008-05-09--reg_4bit

2009-03-10T14:40:07+08:00

library ieee;
library altera;
use altera.altera_primitives_components.all;
use ieee.std_logic_1164.all;
entity reg_4bit is

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2008-05-09--3-bit 並聯載入暫存器(5秒閃一次)

2009-03-10T14:39:48+08:00

library ieee;
library altera;
use altera.altera_primitives_components.all;
use ieee.std_logic_1164.all;

entity reg_3bit is

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2008-04-16--Mealy Model

2009-03-10T14:39:36+08:00

library ieee;
library altera;
use altera.altera_primitives_components.all;
use ieee.std_logic_1164.all;
entity Mealy1 is

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2008-04-11--moore model

2009-03-10T14:39:24+08:00

library ieee;
library altera;
use altera.altera_primitives_components.all;
use ieee.std_logic_1164.all;
entity qaz is

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2008-03-28--除以2的24次方的除頻電路(一秒閃一次)

2009-03-10T14:37:51+08:00

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity M1 is
port( CLK:in std_logic;

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2008-03-21--正緣觸發JK正反器

2009-03-10T14:37:35+08:00

library ieee;
use ieee.std_logic_1164.all;
entity JKFF123 is
port(
S,R,clk:in std_logic;

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2008-03-21--WEEK125

2009-03-10T14:35:11+08:00

library ieee;
use ieee.std_logic_1164.all;
entity week125 is
port(
clk,j,k:in std_logic;

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2008-03-21--Master-Slave Flip-Flop

2009-03-10T14:34:52+08:00

library ieee;
use ieee.std_logic_1164.all;
entity MSFF is
port(
S,R,C:in std_logic;

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